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2.7 ghz dds-based agile rf tm synthesizer AD9956 rev. 0 in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . s p ecificatio n s subj ec t to ch an g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2004 analog de vices, i n c. al l r i ght s r e ser v ed . fea t ures 400 msps int e r n al dds clock speed 48-bit fre q uen c y tuning wo rd 14-bit programmable phase offset integrated 14-bit dac excellent dyna mic performance phase no ise 1 35 dbc/hz @ 1 khz o ffset ?80 db sfdr @ 160 m hz ( 10 0 khz offset i out ) 25 mb/s write-s p eed seria l i/o control 200 mh z phase frequ e ncy det e ctor inputs 655 mh z programmable input divi ders for th e phase frequency dete ctor (m, n) { m , n = 1..16} (b ypassable) programmable rf di vider (r) {r = 1, 2, 4, 8} ( b ypassable) 8 phase/freque ncy profiles 1.8 v supply for device operation 3.3 v supply for i/o and charge pump software contr o lled power-down 48-lea d lfcsp package automatic line ar freq uency s w eeping capability (in dds) programmable charge pump current (up to 4 ma) phase modul a t i on capability multichip synchronization du al-mode pll lock detect 655 mh z cml- mode pecl-compliant driver applic a t io ns agile lo frequency synthesis fm chirp source for radar and scanning syste m s automotive ra dars test and meas urement e q uip m ent a c ou sto-optic d e v i ce d r iv ers func ti on a l bl ock di a g r a m fr e q u e n c y accumulat or phase accumul a t or phase offset phase offset word ti m i n g a n d c o n tr o l lo g i c phase t o amplitude conversion 14 ftw 48 24 da c r f - d iv id e r r fr o m p llo s c 3 p s < 2: 0> res e t i / o port charg e pump scaler buff e r b u ffe r cp_ o ut cp_ r se t pl l _ l o ck/ sync_ i n i / o _ update sync_ out r e fc lk r e fc lk cml c l o ck dri ve r d r v drv drv_ r set d ac_ rs et io u t io u t sync_ cl k sys cl k del t a frequency tuning word del t a frequency ramp rate sy scl k 3 lock det e ct 48 19 14 dd s c o r e sy s c l k i / o _ r es et o s c i lla to r 16 charg e pump p llr e f / pllref p l losc/ pllosc n 4 m 04806-0-001 fi g u r e 1 .
AD9956 rev. 0 | page 2 of 32 table of contents product overview ............................................................................. 3 specifications ..................................................................................... 4 loop measurement conditions .................................................. 9 absolute maximum ratings .......................................................... 10 esd caution ................................................................................ 10 pin configuration and function descriptions ........................... 11 typical performance characteristics ........................................... 13 typical application circuits .......................................................... 16 application circuit explanations ............................................. 17 general description ....................................................................... 18 dds core ..................................................................................... 18 pll circuitry .............................................................................. 18 cml driver ................................................................................. 19 modes of operation ....................................................................... 20 dds modes of operation ......................................................... 20 synchronization modes for multiple devices .............................. 20 serial port operation ..................................................................... 22 instruction byte .......................................................................... 23 serial interface port pin description ....................................... 23 msb/lsb transfers .................................................................... 23 register map and description ...................................................... 24 control function register descriptions ................................. 27 outline dimensions ....................................................................... 32 ordering guide .......................................................................... 32 revision history 7/04revision: initial version
AD9956 rev. 0 | page 3 of 32 product overview the AD9956 is analog devices newest agile rf synthesizer. the device is comprised of dds and pll circuitry. the dds features a 14-bit dac operating at up to 400 msps and a 48-bit frequency tuning word (ftw). the pll circuitry includes a phase frequency detector with scaleable 200 mhz inputs (divider inputs operate up to 655 mhz) and digital control over the charge pump current. the device also includes a 655 mhz cml-mode pecl-compliant driver with programmable slew rates. the AD9956 uses advanced dds technology, an internal high speed, high performance dac, and an advanced phase frequency detector/charge pump combination, which, when used with an external vco, enables the synthesis of digitally programmable, frequency-agile analog output sinusoidal wave- forms up to 2.7 ghz. the AD9956 is designed to provide fast frequency hopping and fine tuning resolution (48-bit frequency tuning word). information is loaded into the AD9956 via a serial i/o port that has a device write-speed of 25 mb/s. the AD9956 dds block also supports a user-defined linear sweep mode of operation. the AD9956 is specified to operate over the extended automotive range of ?40c to +125c.
AD9956 rev. 0 | page 4 of 32 specifications avdd = dvdd = 1.8 v 5%; dvdd_i/o = cp_vdd = 3.3 v 5% (@ t a = 25c) dac_r set = 3.92 k?, cp_r set = 3.09 k?, drv_r set = 4.02 k?, unless otherwise noted. table 1. parameter min typ max unit test conditions/comments rf divider (refclk ) input section (r) rf divider input range 1 2700 mhz dds sysclk not to exceed 400 msps input capacitance (dc) 3 pf input impedance (dc) 1500 ? input duty cycle 42 50 58 % input power/sensitivity ?10 +4 dbm single-ended, into a 50 ? load 1 input voltage level 350 1000 mv p-p phase frequency detector/charge pump pllref input input frequency 2 m set to divide by at least 4 655 mhz m bypassed 200 mhz input voltage levels 200 450 600 mv p-p input capacitance 10 pf input resistance 1500 ? pllosc input input frequency n set to divide by at least 4 655 mhz n bypassed 200 mhz input voltage levels 200 450 600 mv p-p input capacitance 10 pf input resistance 1500 ? charge pump source/sink maximum current 4 ma charge pump source/sink accuracy ?15 +5 % charge pump source/sink matching ?5 +5 % charge pump output compliance range 3 0.5 cp_vdd ? 0.5 v pll_lock drive strength 2 ma phase frequency detector noise floor @ 50 khz pfd frequency 149 dbc/hz @ 2 mhz pfd frequency 133 dbc/hz @ 100 mhz pfd frequency 116 dbc/hz @ 200 mhz pfd frequency 113 dbc/hz cml output driver (drv) differential output voltage swing 4 720 mv 50 ? load to supply, both lines maximum toggle rate 655 mhz common-mode output voltage 1.75 v output duty cycle 42 50 58 % output current continuous 5 7.2 ma rising edge surge 20.9 ma falling edge surge 13.5 ma output rise time 250 ps 100 ? terminated, 5 pf load
AD9956 rev. 0 | page 5 of 32 parameter min typ max unit test conditions/comments logic inputs (sdi/o, i/o_reset, reset, i/o_update, ps0 to ps2, sync_in) v ih , input high voltage 2.0 v v il , input low voltage 0.8 v i inh , i inl input current 1 5 a c in , maximum input capacitance 3 pf logic outputs (sdo, sync_out, pll_lock) 6 v oh , output high voltage 2.7 v v oh , output low voltage 0.4 v i oh 100 a i ol 100 a power consumption total power consumed, all functions on 400 mw iavdd 85 ma idvdd 45 ma idvdd_i/o 20 ma icp_vdd 15 ma power-down mode 80 mw wake-up time (from power-down mode) digital power-down (cfr1<7>) 12 ns dac power-down (cfr2<39>) 7 s rf divider power-down (cfr2<23>) 400 ns clock driver power-down (cfr2<20>) 6 s charge pump full power-dow n (cfr2<4>) 10 s charge pump quick power-down (cfr2<3>) 150 ns dac output characteristics resolution 14 bits full-scale output current 10 15 ma gain error ?10 +10 % fs output offset 0.6 a output capacitance 5 pf voltage compliance range avdd ? 0.50 avdd + 0.50 v wideband sfdr (dc to nyquist) 10 mhz analog out ?64 dbc 40 mhz analog out ?62 dbc 80 mhz analog out ?60 dbc 120 mhz analog out ?55 dbc 160 mhz analog out ?55 dbc narrowband sfdr 10 mhz analog out (1 mhz) ?89 dbc 10 mhz analog out (250 khz) ?91 dbc 10 mhz analog out (50 khz) ?93 dbc 40 mhz analog out (1 mhz) ?87 dbc 40 mhz analog out (250 khz) ?89 dbc 40 mhz analog out (50 khz) ?91 dbc 80 mhz analog out (1 mhz) ?85 dbc 80 mhz analog out (250 khz) ?87 dbc 80 mhz analog out (50 khz) ?89 dbc 120 mhz analog out (1 mhz) ?83 dbc 120 mhz analog out (250 khz) ?85 dbc 120 mhz analog out (50 khz) ?87 dbc
AD9956 rev. 0 | page 6 of 32 parameter min typ max unit test conditions/comments 160 mhz analog out (1 mhz) ?81 dbc 160 mhz analog out (250 khz) ?83 dbc 160 mhz analog out (50 khz) ?85 dbc dac residual phase noise 19.7 mhz f out @ 10 hz offset 125 dbc/hz @ 100 hz offset 135 dbc/hz @ 1 khz offset 143 dbc/hz @ 10 khz offset 152 dbc/hz @ 100 khz offset 158 dbc/hz >1 mhz offset 163 dbc/hz 51.84 mhz f out @ 10 hz offset 119 dbc/hz @ 100 hz offset 125 dbc/hz @ 1 khz offset 132 dbc/hz @ 10 khz offset 142 dbc/hz @ 100 khz offset 150 dbc/hz >1 mhz offset 155 dbc/hz 105.3 mhz analog out @ 10 hz offset 105 dbc/hz @ 100 hz offset 115 dbc/hz @ 1 khz offset 122 dbc/hz @ 10 khz offset 131 dbc/hz @ 100 khz offset 139 dbc/hz >1 mhz offset 142 dbc/hz 155.52 mhz analog out @ 10 hz offset 105 dbc/hz @ 100 hz offset 110 dbc/hz @ 1 khz offset 119 dbc/hz @ 10 khz offset 127 dbc/hz @ 100 khz offset 135 dbc/hz >1 mhz offset 142 dbc/hz crystal oscillator (on pllref input) operating range 20 25 30 mhz residual phase noise (@ 25 mhz) @ 10 hz offset 95 dbc/hz @ 100 hz offset 120 dbc/hz @ 1 khz offset 137 dbc/hz @ 10 khz offset 156 dbc/hz @ 100 khz offset 164 dbc/hz >1 mhz offset 170 dbc/hz digital timing specifications cs to sclk setup time tpre 6 ns period of sclk (write speed) tsclkw 40 ns period of sclk (read speed) tsclkr 400 ns serial data setup time tdsu 6.5 ns serial data hold time tdhld 0 ns tdv data valid time tdv 40 ns i/o update to sync_clk setup time tud 7 ns ps<2:0> to sync_clk setup time tps 7 ns
AD9956 rev. 0 | page 7 of 32 parameter min typ max unit test conditions/comments latencies/pipeline delays 7 i/o update to dac frequency change 33 sysclk cycles i/o update to dac phase change 33 sysclk cycles ps<2:0> to dac frequency change 29 sysclk cycles ps<2:0> to dac phase change 29 sysclk cycles i/o update to cp_out scaler change 4 sysclk cycles i/o update to frequency accumulator step size change 4 sysclk cycles i/o update to frequency accumulator ramp rate change 4 sysclk cycles rf divider/cml driver equivalent intrinsic time jitter f in = 414.72 mhz, f out = 51.84 mhz bw = 12 khz ?> 400 khz 136 f s rms oc1, rf divider r = 8 f in = 1244.16 mhz, f out = 155.52 mhz bw = 12 khz ?> 1.3 mhz 101 f s rms oc3, rf divider r = 8 f in = 2488.32 mhz, f out = 622.08 mhz bw = 12 khz ?> 5 mhz 108 f s rms oc12, rf divider r = 4 rf divider/cml driver residual phase noise f in = 157.6 mhz, f out = 19.7 mhz rf divider r = 8 @ 10 hz ?115 dbc/hz @ 100 hz ?126 dbc/hz @ 1 khz ?134 dbc/hz @ 10 khz ?143 dbc/hz @ 100 khz ?150 dbc/hz > 1 mhz ?151 dbc/hz f in = 1240 mhz, f out = 155 mhz rf divider r = 8 @ 10 hz ?111 dbc/hz @ 100 hz ?122 dbc/hz @ 1 khz ?129 dbc/hz @ 10 khz ?138 dbc/hz @ 100 khz ?146 dbc/hz @ 1 mhz ?150 dbc/hz >3 mhz ?153 dbc/hz f in = 2488mhz, f out = 622 mhz rf divider r = 4 @ 10 hz ?97 dbc/hz @ 100 hz ?110 dbc/hz @ 1 khz ?120 dbc/hz @ 10 khz ?126 dbc/hz @ 100 khz ?136 dbc/hz @ 1 mhz ?141 dbc/hz >3 mhz ?144 dbc/hz total system time jitter for 622 mhz clock see the loop measurement condi- tions section 12 khz to 5 mhz bandwidth 0.7 ps rms
AD9956 rev. 0 | page 8 of 32 parameter min typ max unit test conditions/comments total system jitter and phase noise for 105.33 mhz adc clock generation circuit see the loop measurement condi- tions section converter limiting jitter 0.53 ps rms resultant snr 67 db phase noise of fundamental @ 10 hz offset ?75 dbc/hz @ 100 hz offset ?87 dbc/hz @ 1 khz offset ?93 dbc/hz @ 10 khz offset ?105 dbc/hz @ 100 khz offset ?145 dbc/hz @ 1 mhz offset ?152 dbc/hz 1 the input impedance of the refclk input is 1500 ?. however, in order to provide match ing on the clock line, an external 50 ? l oad is used. 2 driving the pllref input buffer, the crystal oscillator section of this input stage performs up to only 30 mhz. 3 the charge pump output compliance range is functionally 0.2 v to (cp_vdd ? 0.2 v). the value listed here is the compliance ran ge for 5% matching. 4 measured as peak-to-peak from drv to drv . 5 for a 4.02 k? resistor from drv_rset to gnd. 6 assumes a 1 ma load. 7 i/o_update/ps<2:0> are detected by the AD9956 synchronous to the rising edge of sync_clk. each latency measurement is from the first sync_clk rising edge after the i/o_update/ps<2:0> state change.
AD9956 rev. 0 | page 9 of 3 2 l o op measurement c o nditions 622 mhz oc-1 2 clock v c o = s i r e nza 190-640t ref e r e nce = w e nze l 500-10116 (30.3 mh z) l o o p f i l t er = 10 kh z b w , 60 phas e m a rg in c1 = 170 nf , r1 = 14.4 ?, c2 = 5.11 f , r2 = 89 .3 ?, c3 omi t t e d cp_o ut = 4 ma (s caler = 8) r = 2, m = 1, n = 1 105 mhz conv erter clock v c o = s i r e nza 190-845t ref e r e nce = w e nze l 500-10116 (30.3 mh z) l o o p f i l t er = 10 khz b w , 45 phas e m a rg in c1 = 117 nf , r1 = 28 ?, c2 = 1. 6 f , r2 = 57.1 ?, c3 = 53.4 nf cp_o ut = 4 ma (s caler = 8) r = 8, m = 1, n = 1 c1 c3 input output c2 r1 r2 04806-0-033 fi g u r e 2 . g e n e r i c lo o p fi l t e r
AD9956 rev. 0 | page 10 of 32 absolute maximum ra tings t a bl e 2. p a r a m e t e r r a t i n g analog supply voltage (avdd) 2 v digital supply voltage (dvdd) 2 v digital i/o supp ly voltage (dvdd_i/0) 3.6 v charge pump supply voltage (cpvdd ) 3.6 v maximum digital input voltage ?0.5 v to dvdd _i/o + 0.5 v storage temperature ?65c to +150c operating tem p erature range ?40c to +125c lead temperature range (sol dering 10 s e c) 300c junction tempe r ature 150c t h ermal resista n ce ( ja ) 2 6 c / w s t r e s s es a b o v e t h os e lis t e d u n de r a b s o l u t e m a xi m u m r a t i n g s ma y c a us e p e r m a n en t dama ge t o t h e de vice . this is a s t r e s s ra t i n g onl y ; f u n c t i o n al o p era t ion o f t h e de vice a t t h es e o r an y o t h e r con d i t io ns a b o v e t h o s e i ndic a te d i n t h e op er a t io na l s e c t io n o f t h is sp e c if ic a t io n is no t im plie d . e x p o sur e t o a b s o l u te max i m u m ra t i ng co ndi t i on s fo r ex ten d e d p e r i o d s ma y a f fe c t de vice r e l i ab i l i t y . esd c a ution esd (electrostatic discharge) sensitive device. ele c tr ostatic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharg e wit h out detection. althou gh this product features proprietary esd protection circu i try, permanent damage may occur on devices s u bjec ted to high energy elec- trostatic dischar g es. t h erefore, proper esd prec aution s are reco mmended to avoid performanc e degradation or los s of functionality.
AD9956 rev. 0 | page 11 of 32 pin conf igura t ion and fu nction descriptions 13 14 15 16 17 18 19 20 21 22 23 24 sd o sd i/o sc lk cs dv dd_ i/o s y nc_ out p ll_ lock/s y nc_ in i/o_update ps0 ps1 ps2 dgnd 48 47 46 45 44 43 42 41 40 39 38 37 av dd dac_ rs e t drv _ r s e t c p _r set av dd agnd pllosc pllosc pllref pllref av dd agnd 1 2 3 4 5 6 7 8 9 10 11 12 agnd avdd agnd avdd iout iout avdd agnd i/o_reset reset dvdd dgnd nc = no connect cp_vdd agnd drv drv avdd agnd refclk refclk avdd agnd dvdd 35 cp_out 36 34 33 32 31 30 29 28 27 26 25 AD9956 top view (not to scale) pin 1 indicator 04806-0-008 f i g u re 3. 48-l e ad l f csp p i n conf ig ur a t ion n o t e t h a t t h e ex p o s e d p a ddle on t h is p a cka g e i s a n e l e c t r ical c o nn e c t i o n (p i n 49) as w e l l as a t h er mal enhan c e m e n t. f o r t h e de v ice t o fun c ti o n p r o p e r l y , th e pa d d le mu s t b e a t tac h e d t o a n alog gr o u n d .
AD9956 rev. 0 | page 12 of 32 table 3. 48-lead lfcsp pin function description pin no. mnemonic description 1, 3, 8, 26, 30, 34, 37, 43, 49 agnd analog ground. 2, 4, 7, 27, 31, 38, 44, 48 avdd analog core supply (1.8 v). 5 iout dac analog output. 6 iout dac analog complementary output. 9 i/o_reset resets the serial port when synchronization is lo st in communications but does not reset the de- vice itself (active high). when not being used, this pin should be forced low, because it floats to the threshold value. 10 reset master reset. clears all accumulators and returns all registers to their default values (active high). 11, 25 dvdd digital core supply (1.8 v). 12, 24 dgnd digital ground. 13 sdo serial data output. used only when devi ce is programmed for 3-wire serial data mode. 14 sdi/o serial data i/o. when the part is programmed for 3- wire serial data mode, th is is input only; in 2-wire mode, it serves as both the input and output. 15 sclk serial data clock. provides the clock signal for the serial data port. 16 cs active low signal that enables shared serial busses. when brought high, the serial port ignores the serial data clocks. 17 dvdd_i/o digital interface supply (3.3 v). 18 sync_out synchronization clock output. 19 pll_lock/sync_in bidirectional dual function pin. depending on d evice programming, it is either the dds synchro- nization input (allows alignment of multiple subclocks) or the pll lock detect output signal. 20 i/o_update this input pin, when set high, transfers the data fr om the i/o buffers to the internal registers on the rising edge of the internal sync_clk, which can be observed on sync_out. 21 to 23 ps0 to ps2 profile select pins. specify one of eight frequency tuning word/phase offset word profiles. in linear sweep mode, ps0 determines the state of the sweep. in linear sweep no dwell mode, ps0 is a trig- ger that initiates the sweep. ps1 and ps2 have no function during linear sweep mode or linear sweep no dwell mode. 28 refclk rf divider and dds refclk complementary input. 29 refclk rf divider and dds refclk input. 32 drv cml driver complementary output. 33 drv cml driver output. 35 cp_vdd charge pump supply pin (3.3 v). to minimize noise on the charge pump, isolate this supply from dvdd_i/o. 36 cp_out charge pump output. 39 pllref phase frequency detector reference input. 40 pllref phase frequency detector refe rence complementary input. 41 pllosc phase frequency detector oscillator (feedback) complementary input. 42 pllosc phase frequency detector oscillator (feedback) input. 45 cp_rset charge pump current set (program charge pump current with a resistor to agnd). 46 drv_rset cml driver output current set (program cml output current with a resistor to agnd). 47 dac_rset dac output current set (program dac output current with a resistor to agnd). note that the exposed paddle on this package is an electrical connection (pin 49) as well as a thermal enhancement. in order fo r the device to function properly, the paddle must be attached to analog ground.
AD9956 rev. 0 | page 13 of 32 typical perf orm ance cha r acte ristics 04806-0-015 center 10.1mhz 100khz/ span 1mhz ref lvl 0dbm delta 1 [t1] ? 84.82db ?404.80961924khz rbw vbw swt rf att unit 500hz 500hz 20s 20db db 1 ap a ?2 0 ?4 0 0 ?6 0 ?3 0 ?5 0 ?1 0 ?7 0 ?8 0 ?9 0 ?100 1 1 f i g u re 4. a d 99 56 da c p e r f o r m a nce: 4 00 m s ps cl ock , 10 m h z f ou t , 1 mh z span 04806-0-016 center 40.1mhz 100khz/ span 1mhz ref lvl 0dbm delta 1 [t1] ? 78.67db ?100.20040080khz rbw vbw swt rf att unit 500hz 500hz 20s 20db db 1 ap a ?2 0 ?4 0 0 ?6 0 ?3 0 ?5 0 ?1 0 ?7 0 ?8 0 ?9 0 ?100 1 1 f i g u re 5. a d 99 56 da c p e r f o r m a nce: 4 00 m s ps cl ock , 40 m h z f ou t , 1 mh z span 04806-0-017 center 100.1mhz 100khz/ span 1mhz ref lvl 0dbm delta 1 [t1] ? 57.74db ?400.80160321khz rbw vbw swt rf att unit 500hz 500hz 20s 20db db 1 ap a ?2 0 ?4 0 0 ?6 0 ?3 0 ?5 0 ?1 0 ?7 0 ?8 0 ?9 0 ?100 1 1 f i g u re 6. a d 99 56 da c p e r f o r m a nce: 4 00 m s ps cl ock , 10 0 m h z f ou t , 1 m h z sp an 04806-0-018 start 0hz 16.9mhz/ stop 169mhz ref lvl 0dbm delta 1 [t1] ? 67.45db 74.50901804mhz rbw vbw swt rf att unit 10khz 10khz 4.3s 20db db 1 ap a ?2 0 ?4 0 0 ?6 0 ?3 0 ?5 0 ?1 0 ?7 0 ?8 0 ?9 0 ?100 1 1 f i g u re 7. a d 99 56 da c p e r f o r m a nce: 4 00 m s ps cl ock , 10 m h z f ou t , 200 m h z spa n 04806-0-019 start 0hz 20mhz/ stop 200mhz ref lvl 0dbm delta 1 [t1] ? 62.65db 100.20040080mhz rbw vbw swt rf att unit 10khz 10khz 5s 20db db 1 ap a ?2 0 ?4 0 0 ?6 0 ?3 0 ?5 0 ?1 0 ?7 0 ?8 0 ?9 0 ?100 1 1 f i g u re 8. a d 99 56 da c p e r f o r m a nce: 4 00 m s ps cl ock , 40 m h z f ou t , 200 m h z spa n 04806-0-020 start 0hz 20mhz/ stop 200mhz ref lvl 0dbm delta 1 [t1] ? 48.78db ?400.80160321khz rbw vbw swt rf att unit 10khz 10khz 5s 20db db 1 ap a ?2 0 ?4 0 0 ?6 0 ?3 0 ?5 0 ?1 0 ?7 0 ?8 0 ?9 0 ?100 1 1 f i g u re 9. a d 99 56 da c p e r f o r m a nce: 4 00 m s ps cl ock , 10 0 m h z f ou t , 2 00 m h z sp an
AD9956 rev. 0 | page 14 of 32 04806-0-021 center 159.5mhz 100khz/ span 1mhz ref lvl 0dbm delta 1 [t1] ? 78.13db ?100.20040080khz rbw vbw swt rf att unit 500khz 500khz 20s 20db db 1 ap a ?2 0 ?4 0 0 ?6 0 ?3 0 ?5 0 ?1 0 ?7 0 ?8 0 ?9 0 ?100 1 1 f i g u re 10. a d 9 9 5 6 da c p e r f or ma nc e: 40 0 m s ps c l o c k , 16 0 m h z f ou t , 1 m h z sp an frequency (hz) l(f) (dbc / h z) 0 ?10 ?20 ?30 ?40 ?60 ?50 ?70 ?80 ?90 ? 100 ? 110 ? 130 ? 120 ? 140 ? 160 ? 150 ? 170 10 1k 100 10k 100k 1m 04806-0-023 f i gur e 1 1 . ad99 56 dds/ d a c re si dual p h a s e no i s e 40 0 m h z c l o c k , 10 m h z o u t p ut frequency (hz) l(f) (dbc / h z) 0 ?1 0 ?2 0 ?3 0 ?4 0 ?6 0 ?5 0 ?7 0 ?8 0 ?9 0 ?100 ?110 ?130 ?120 ?140 ?160 ?150 ?170 10 1k 100 10k 100k 1m 04806-0-024 f i gur e 1 2 . ad99 56 dds/ d a c re si dual p h a s e no i s e 40 0 m h z c l o c k , 40 m h z o u t p ut 04806-0-022 start 0hz 20mhz/ stop 200mhz ref lvl 0dbm delta 1 [t1] ? 56.33db ? 80.96192385mhz rbw vbw swt rf att unit 10khz 10khz 5s 20db db 1 ap a ?2 0 ?4 0 0 ?6 0 ?3 0 ?5 0 ?1 0 ?7 0 ?8 0 ?9 0 ?100 1 1 f i g u re 13. a d 9 9 5 6 da c p e r f or ma nc e: 40 0 m s ps c l o c k , 16 0 m h z f ou t , 2 00 m h z sp an frequency (hz) l(f) (dbc / h z) 0 ?1 0 ?2 0 ?3 0 ?4 0 ?6 0 ?5 0 ?7 0 ?8 0 ?9 0 ?100 ?110 ?130 ?120 ?140 ?160 ?150 ?170 10 1k 100 10k 100k 10m 1m 04806-0-025 f i gur e 1 4 . ad99 56 dds/ d a c re si dual p h a s e no i s e 40 0 m h z c l o c k , 10 3 m h z o u t p ut frequency (hz) l(f) (dbc / h z) 0 ?1 0 ?2 0 ?3 0 ?4 0 ?6 0 ?5 0 ?7 0 ?8 0 ?9 0 ?100 ?110 ?130 ?120 ?140 ?160 ?150 ?170 10 1k 100 10k 100k 10m 1m 04806-0-026 f i gur e 1 5 . ad99 56 dds/ d a c re si dual p h a s e no i s e 40 0 m h z c l o c k , 15 9 m h z o u t p ut
AD9956 rev. 0 | page 15 of 32 frequency (hz) l(f) (dbc / h z) 0 ?1 0 ?2 0 ?3 0 ?4 0 ?6 0 ?5 0 ?7 0 ?8 0 ?9 0 ?100 ?110 ?130 ?120 ?140 ?160 ?150 ?170 10 1k 100 10k 100k 10m 1m 04806-0-027 f i gure 16. r f d i v i d e r and c m l d r iver r e s i dua l p h a s e no i s e (840 mhz in, 105 mh z o u t) frequency (hz) l(f) (dbc / h z) 0 ?1 0 ?2 0 ?3 0 ?4 0 ?6 0 ?5 0 ?7 0 ?8 0 ?9 0 ?100 ?110 ?130 ?120 ?140 ?160 ?150 ?170 10 1k 100 10k 100k 10m 1m 04806-0-028 f i gure 17. r f d i v i d e r and c m l d r iver r e s i dua l p h a s e no i s e (124 0 mhz in, 155 mh z o u t) frequency (hz) l(f) (dbc / h z) 0 ?1 0 ?2 0 ?3 0 ?4 0 ?6 0 ?5 0 ?7 0 ?8 0 ?9 0 ?100 ?110 ?130 ?120 ?140 ?160 ?150 ?170 10 1k 100 10k 100k 10m 1m 04806-0-029 f i gure 18. r f d i v i d e r and c m l d r iver r e s i dua l p h a s e no i s e (168 0 mhz in, 210 mh z o u t) frequency (hz) l(f) (dbc / h z) 0 ?1 0 ?2 0 ?3 0 ?4 0 ?6 0 ?5 0 ?7 0 ?8 0 ?9 0 ?100 ?110 ?130 ?120 ?140 ?160 ?150 ?170 10 1k 100 10k 100k 100m 10m 1m 04806-0-030 f i gure 19. r f d i v i d e r and c m l d r iver r e s i dua l p h a s e no i s e (248 8 mhz in, 622 mh z o u t) frequency (hz) l(f) (dbc / h z) 0 ?1 0 ?2 0 ?3 0 ?4 0 ?6 0 ?5 0 ?7 0 ?8 0 ?9 0 ?100 ?110 ?130 ?120 ?140 ?160 ?150 ?180 ?170 10 1k 100 10k 100k 10m 1m 04806-0-031 f i gure 20. t o t a l s y s t em p h as e n o is e f o r 1 0 5 mh z co n v e r ter c l o c k frequency (hz) l(f) (dbc / h z) 0 ?1 0 ?2 0 ?3 0 ?4 0 ?6 0 ?5 0 ?7 0 ?8 0 ?9 0 ?100 ?110 ?130 ?120 ?140 ?160 ?150 ?180 ?170 10 1k 100 10k 100k 10m 1m 04806-0-032 f i g u re 21. t o t a l sy s t em p h as e n o is e f o r 6 2 2 m h z o c -1 2 c l ock
AD9956 rev. 0 | page 16 of 32 typical applica t ion circuits da c pllref pllosc cp_out dds n m r lpf vco cml driver phase frequency detector/charge pump 25mhz crystal 400mhz clock1 clock1 AD9956 04806-0-010 lpf f i g u re 22. d u al- c l o ck conf ig ur at io n pllref pllosc cp_out dds r vco AD9956 04806-0-011 lpf lpf dac f i g u re 23. f r ac t i on al-d iv ide r l o op pllref pllosc cp_out dds r vco AD9956 04806-0-012 lpf dac n cml driver 2.5ghz tone 8-level fsk (fc = 100mhz) bpf bpf 25mhz crysta l f i gure 24. l o and b a seband modu lation g e ner a tion
AD9956 rev. 0 | page 17 of 32 da c c harg e pump ref osc dds n m r lpf vco cml driver phase frequency detector external reference 622mhz clock1 clock2 AD9956 04806-0-013 f i g u re 25. o p t i c a l net w ork i ng cl ock char ge pump pllref pllosc n vco dac dds phase frequency detector 650mhz 04806-0-014 lpf lpf f i gu r e 2 6 . dir e ct up c o n v er si on applic a t io n circui t e x pl ana t i o ns d u a l -c l o ck c o nf i g ur a t i o n i n this lo o p , m = 1, n = 16, a n d r = 4. th e dds t u ning w o r d is al so eq ual t o ? so th a t t h e f r eq ue n c y o f c l o c k 1 eq ual s t h e f r e q uen c y o f clo c k 1. ph as e ad j u st m e n t s i n t h e dds p r o v ide a 14-b i t p r og ramma b l e r i sin g e d g e sk ew c a p a b i li ty o f cl o c k 1 wi t h r e s p ec t t o cl o c k 1 (s ee f i gur e 22). fr a c t i o n a l - d i v i d e r l o o p t h i s l o op of f e r s t h e pre c i s e f r e q u e nc y d i v i s i on ( 4 8 - bit ) of t h e d d s in t h e f e e d bac k p a t h as wel l as th e f r eq uenc y sw eep i n g c a p a b i l i t y of t h e dd s . pro g r a mming t h e dd s t o s w e e p f r om 24 mh z t o 25 mh z s w eeps t h e o u t p u t o f th e v c o f r o m 2.7 gh z t o 2.6 gh z. the r e f e r e n c e in this cas e is a sim p le cr ys tal (s ee f i gur e 23). lo a n d ba s e b a n d m o d u l a ti o n g e ner a ti o n u s in g t h e ad99 56 s p ll s e c t io n t o g e n e r a t e an l o an d t h e dds p o r t io n to gen e r a te a m o d u la te d b a s e b a nd, t h is cir c ui t us es a n ext e r n al mixer t o p e r f o r m s o m e sim p le m o d u l a t i on a t r f f r eq ue n c i e s (see f i gur e 24). o p ti c a l n e two r k i n g c l o c k this is t h e ad9 956 co nf igur ed as a n o p t i cal n e tw o r kin g c l o c k. the lo o p can be us ed t o g e n e ra te a 622 mh z c l o c k f o r o c 12. the dds c a n b e p r og ra mm e d to o u t p u t 8 khz t o s e r v e as a b a s e re f e re nc e f o r ot he r c i rc u i t s i n t h e s u b s y s t e m ( s e e f i g u re 2 5 ) . dire c t u p con v e r si o n the AD9956 is co nf igur ed t o us e the d d s as a p r ecisio n r e f e r - en c e t o the p ll lo o p . s i n c e the v c o is < 655 mh z, i t can be fed s t ra i g h t i n t o th e p h a s e f r eq ue n c y d e t e ct o r f eed b a c k in p u t (w i t h t h e divider enable d), as s e e n in f i gur e 26.
AD9956 rev. 0 | page 18 of 32 gene ral description dds c o re the dds c a n cre a te dig i t a l phas e r e la t i o n shi p s b y clo c k i n g a 48-b i t acc u m u la t o r . th e i n cr emen t a l va l u e lo ade d i n t o t h e acc u m u l a t o r , k n o w n as t h e f r e q uen c y t u ni n g wo r d , co n t r o ls t h e ove r f l ow r a te of t h e a c c u m u l a to r . si m i l a r to a s i ne w a ve c o m - plet in g a 2 radian r e v o l u t i on, t h e o v er f l o w o f th e acc u m u l a t o r is c y clica l in na t u r e a nd ge n e ra tes a b a s e f r e q uen c y acco r d i n g to th e f o llo w i n g e q ua ti o n . 48 2 ) ( s o f ftw f = } 2 0 { 47 ftw t h e i n s t a n ta n e o u s p h a s e o f th e s i n e w a v e i s , th er e f o r e , th e o u t - p u t o f t h e ph as e acc u m u l a to r b l o c k. this sig n a l ca n b e ph as e - o f fs et b y p r o g r a mmin g a n a d d i t i ve dig i t a l ph as e adde d to e a ch a nd e v er y phas e s a m p le co min g o u t o f t h e acc u m u l a t o r . t h ese i n s t a n ta n e o u s p h a s e v a l u e s a r e th en p i pe d th r o u gh a phas e- t o -am p li t u de co n v ersio n (s o m et i m es cal l e d an a n g l e - to - a m p l i tu d e c o n v e r s i on or a a c ) bl o c k . t h i s a l gor i t h m f o l l ows a co s(x) r e la tio n s h i p w h e r e x is t h e phas e comin g o u t o f t h e phas e o f fs et b l o c k, n o r m ali z e d to 2. f i nal l y , t h e am pli t ude w o r d s a r e p i p e d t o a 14 -b i t d a c. b e c a us e t h e d a c is a s a m p le d da t a sys tem, t h e o u t p u t i s a r e co n s t r uc t e d s i n e w a v e th a t n eed s t o be f i l t e r ed t o tak e h i gh f r eq ue n c y ima g es o u t o f t h e s p e c t r um. th e d a c is a c u r r en t- s t e e r i n g d a c t h a t is a v d d r e fer e n c e d . t o g et a m e as ur a b le v o l t a g e output , t h e d a c output s m u s t te r m i n ate t h rou g h a l o a d re s i sto r t o a v d d , typ i c a l l y 50 ?. a t p o si t i v e f u l l s c al e , i o ut sinks n o c u r r en t a nd t h e v o l t a g e dr o p acros s t h e lo ad r e sis t o r is zer o . ho w e v e r , t h e iou t o u t p u t sinks t h e d a c s p r og ra mm e d f u l l - s c ale o u t p u t c u r r en t, c a usin g t h e maxim u m o u t p u t v o l t a g e t o d rop a c ro ss t h e l o a d re s i stor . a t ne g a t i v e f u l l - s c a l e , t h e s i tu a t i o n is r e v e rs e d and i o ut si nks t h e f u l l -s cale c u r r en t (an d g e nera tes t h e m a x i m u m d rop a c ro ss t h e l o a d re s i stor ) . a t t h e s a m e t i me, iou t s i n k s no c u r r e n t ( a n d ge ne r a te s no vo lt ag e d r o p ) . a t mids cale , t h e o u t p u t s sink e q ual a m o u n t s o f c u r r en t, g e n e ra t i n g e q u a l vo lt age d rop s . pll cir c uitr y the AD9956 inc l udes a n rf divider (di v ide-b y -r), a p h as e f r e q uen c y det e c t o r , a n d a p r og ra mma b l e o u t p ut c u r r en t cha r g e p u m p . i n co r p o r a t in g t h es e b l o c ks t o g e t h er , us er s ca n g e n e r a te ma n y us ef u l circ ui ts fo r f r e q uen c y syn t h e sis. a fe w sim p le exa m ples a r e sho w n i n t h e t y p i cal a p plic a t ion cir c ui ts. the rf divi der accep t s dif f er en t i a l o r sin g le- e nde d sig n a l s u p to 2.7 gh z. th e r f di vi der als o s u p p lies t h e s y s c lk i n p u t t o t h e d d s. b e ca us e th e d d s op era t es u p t o o n l y 400 ms ps, de vice f u n c tion r e q u ires tha t f o r a n y rf in p u t sig n al > 400 mh z, t h e rf divider b e e n ga ge d . t h e rf divider can b e pr o g r a mm e d to tak e val u es o f 1, 2, 4, o r 8. t h e ra tio f o r th e di vid e r is p r o- g r a m m e d i n t h e co n t r o l r e g i ster . the o u tp u t o f t h e divider c a n b e r o u te d t o t h e in p u t o f t h e on-chi p cm l dr i v er . f o r lo w e r f r e q uen c y in p u t sig n als, i t is p o ssi b l e t o us e t h e divider t o di vide t h e i n p u t sig n al t o t h e cm l dr iv er a nd us e t h e un di v i de d in p u t o f t h e divi der as t h e s y s c lk in p u t t o t h e d d s, o r vice v e rs a . i n al l cas e s, t h e c l o c k t o the d d s sh o u ld n o t excee d 400 ms ps. the o n -chi p phas e f r e q uen c y det e c t o r has tw o dif f er en t i al in p u ts, p llref (th e r e f e r e n c e in p u t) and p llosc (th e f e e d - b a ck o r os ci l l a t o r in p u t). th es e dif f er en t i al in pu ts can b e dr i v e n b y sin g le-e n d e d sig n als; h o w e v e r , wh en do in g s o , t i e t h e u n us e d in p u t thr o u g h a 100 pf ca p a ci t o r t o th e a n alog su p p l y (a vd d). the maxi m u m s p e e d o f t h e phas e f r e q uen c y det e c t o r i n p u ts is 200 mh z. e a c h o f th e in p u ts has a b u f f er a nd a divider (m o n p l lref an d n o n pll o sc) tha t o p er a t es a t u p t o 655 mh z. i f th e sig n al exc eeds 200 mh z, h o w e v e r , the divider m u s t be u s ed . t h e d i v i d e r s a r e p r o g r a m m ed th r o u g h th e co n t r o l r e g i s t e r s and t a k e an y i n teger v a l u e b e twe e n 1 and 16. the p l l r ef in p u t als o has t h e o p t i o n o f en ga g i n g a n in-li n e os cil l a t o r cir c ui t. en ga g i n g t h is cir c ui t m e a n s tha t t h e p l lref in p u t can be dr iv en wi t h a cr ys tal in t h e o f 20 mh z p l lref 30 mh z ra n g e . t h e ch ar ge pu m p output s a c u r r e n t i n re sp on s e to an e r ror sig n al g e n e r a t e d in t h e phas e f r e q uen c y det e c t o r . th e o u t p u t c u r r e n t i s pro g r a m m e d t h rou g h by pl a c i n g a re s i stor ( c p _ r set ) f r o m t h e cp _r s e t p i n t o g r o u nd . th e val u e is dic t a t e d b y t h e f o ll o w i n g eq ua tio n : set cp_r cp_out 1.55 = this s ets t h e cha r g e p u m p s r e fer e n c e o u t p ut c u r r en t. a l s o , a p r ogra m m a b l e scale r m u l t i p li es th i s ba se v a l u e b y a n y i n t e g e r f r o m 1 t o 8, p r og ra mma b l e t h r o ug h t h e cp c u r r en t s c ale b i ts in t h e c o n t r o l f u nc t i o n r e g i s ter 2, cfr2<2:0>.
AD9956 rev. 0 | page 19 of 32 cml driver f o r clo c k i n g a pplica t ion s , a n on-ch i p c u r r en t m o d e log i c (cml) dr i v er is in cl ud e d . this cml dr i v er ge nera t e s v e r y lo w ji t t er clo c k e d g e s. th e ou t p u t s of t h e cml dr i v er a r e c u r r en t o u t p u t s an d dr i v es p e cl leve ls when ter mina t e d in t o a 100 ? lo ad . th e b a s e ou t p ut c u r r en t o f t h e dr i v er is p r og ra mm e d b y a t t a ch i n g a re s i s t or f rom t h e dr v _ r s e t pi n to g rou nd ( n om i - nal l y 4.02 k? f o r a co n t in uo us c u r r en t o f 7.2 ma). an o p tio n al on - c h i p c u r r e n t pro g r a m m i ng re s i stor i s e n abl e d by s e tt i n g a bit in t h e con t r o l r e g i s t er . the r i sin g e d g e and fal l i n g e d g e s l e w ra t e s a r e in depen d en tl y p r ogra m m a b l e t o h e l p co n t r o l o v er - s h o o t an d r i n g i n g t h r o ug h t h e a p plic a t ion o f surg e c u rr en t d u r i n g r i sin g e d g e t r a n si t i o n s and fal l in g e d g e t r a n si t i o n s (s e e f i gur e 27). th ere is a def a u l t s u rg e c u r r en t o f 7.6 ma on t h e ri s i n g ed g e a n d 4. 05 m a o n th e falli n g ed g e . b i ts i n t h e co n t r o l r e g i ster ena b le a ddi t i ona l r i sin g e d ge and fa l l in g e d ge surge c u r r en t, as w e l l dis a b l e t h e def a u l t s u rg e c u r r en t (s e e t h e c o n t r o l f u n c ti o n re gi s t e r descri p t i o n s secti o n f o r d e ta ils ) . t h e cml dr i v er can b e dr i v e n b y t h e ? rf divider i n p u t ? rf divider o u t p u t ? pl lo s c in pu t i( t) t ~25 0 ps ~25 0 ps ri s i ng e d ge sur g e continuous falling edge surge continuous 04806-0-002 f i gure 2 7 . r i si ng e d ge a n d f a ll i n g e d ge sur g e c u rr ent o u tput o f the c m l cl o c k d r i v er , as o p p o sed to th e steady sta t e conti n u o us cur r ent
AD9956 rev. 0 | page 20 of 32 modes of operation dds modes of operation single-tone mode this is the default mode of operation for the dds core. the phase accumulator runs at a fixed frequency, as per the active profiles tuning word. likewise, any phase offset applied to the signal is a static value, which comes from the phase offset word of the active profile. the device has eight different phase/fre- quency profiles, each with its own 48-bit frequency tuning word and 14-bit phase offset word. profiles are selected by applying their digital value on the profile-select pins (ps2, ps1, and ps0). it is impossible to use the phase offset of one profile and the frequency tuning word of another. linear sweep mode this mode is entered by setting the linear sweep enable bit in the control register (cfr1<17> = 1) but leaving the linear sweep no dwell bit clear (cfr1<16> = 0). when the part is in linear sweep mode, the frequency accumulator ramps the output frequency of the device from a programmed lower frequency to a programmed upper frequency or from the upper frequency to the lower frequency. the lower frequency is set by the frequency tuning word stored in profile 0, and the upper frequency is set by the frequency tuning word stored in profile 1. the combinational logic within the frequency accumulator requires that the value stored at ftw0 must always be less than the value stored in ftw. the direction of the sweep (sweep up to ftw1, sweep down to ftw0) is controlled by the ps0 pin. a high state on this pin tells the part to sweep up to ftw1. a low state on this pin tells the part to sweep down to ftw0. the frequency accumulator requires four values, which are stored in the register map. first, it requires an incremental frequency value that tells the frequency accumulator how big of a fre- quency step to take each time it takes a step when ramping up. this value is stored in the rising delta frequency tuning word (rdftw). the second value required is the rate at which the frequency accumulator should increment, that is, how often it should take a step. this value is stored in the rising sweep ramp rate word (rsrr). the rsrr value specifies the number of sync_clk cycles the frequency accumulator should count between steps. the third and fourth values are the falling ramp equivalents, the falling delta frequency tuning word (fdftw) and the falling sweep ramp rate (fsrr). when operating in the linear sweep default mode, combina- tional logic ensures that the part never ramps up past ftw1, even if the next rdftw increments the frequency past ftw1. once it reaches ftw1, as long as the ps0 pin stays high, the frequency remains at ftw1. likewise, the internal logic ensures that the part never ramps down past ftw0, even if the next rdftw increments the frequency past ftw0. during a sweep down (ps0 = 0), once the part reaches ftw0, as long as the ps0 pin stays low, the frequency remains at ftw0. if a sweep is interrupted and the state of the ps0 pin is changed during the midst of a sweep, the part begins sweeping in the new direction at the rate dictated by the relevant delta fre- quency tuning word and sweep ramp rate word. for example, if the part is programmed to sweep from 100 mhz to 140 mhz and to take 1 khz steps every 1000 sync clock cycles (rising and falling sweep words are the same), it would take four seconds to complete a sweep. if the ps0 has been low for a very long time (more than four seconds), changing the ps0 pin to high starts a sweep up to 140 mhz. if after two seconds (not enough time for a full sweep in this example) the ps0 pin is brought low again, the part begins sweeping down from the current value, roughly 120 mhz. linear sweep no dwell mode this mode is entered by setting the linear sweep enable bit and the linear sweep no dwell bit in the control register (cfr<17:16> =1). when the part is in linear sweep no dwell mode, the frequency accumulator ramps the output frequency of the device from a programmed lower frequency to a pro- grammed upper frequency. upon reaching the upper frequency, the accumulator returns to the lower frequency directly, without ramping back down. unlike the default mode of the linear sweep, this mode uses only the rising delta frequency tuning word (rdftw) and the rising sweep ramp rate (rsrr). the operation is still controlled by the ps0 pin. in this mode, how- ever, it acts as a trigger for the sweep, not a direction bit. once a ps0 low-to-high transition is detected, the part completes the entire sweep, regardless of whether or not the ps0 pin is changed back to low during the sweep. after the sweep is com- pleted, another sweep may be initiated by applying another rising edge on the ps0 pin. this means that the ps0 pin needs to be brought low prior to the next sweep. synchronization modes for multiple devices in a dds system, the sync_clk is derived internally off the master system clock, sysclk, with a 4 divider. because the divider does not power up to a known state, it is possible for multiple devices in a system to have staggered clock-phase relationships. this is because each device could potentially gen- erate the sync_clk rising edge from any one of four rising edges of sysclk. this ambiguity can be resolved by employing digital synchronization logic to control the phase relationships of the derived clocks among different devices in the system. it is important to note that the synchronization functions included on the AD9956 control only the timing relationships among different digital clocks. they do not compensate for the analog timing skew on the system clock due to mismatched phase relationships on the input clock, refclk. figure 28 illustrates this concept.
AD9956 rev. 0 | page 21 of 32 automatic s y nchroniz ation i n a u t o ma t i c sy n c hr o n iz a t ion m o d e , t h e d e vi c e is place d i n t o sl a v e mo de and a u tom a t i c a l l y a l i g ns t h e i n te r n a l s y nc _ c l k to a mast er s y n c _clk sig n al , su p p lie d on t h e s y n c _i n in p u t. w h en t h is b i t is ena b le d , t h e pl l_l o c k is n o t a v a i la b l e as a n o u t p ut, h o we ver , a n o u t-o f -lo c k co ndi t i on can b e dete c t e d b y r e a d i n g c o n t r o l f u n c ti o n r e gi s t e r 1 a n d ch ec kin g th e s t a t us o f t h e pll_l o ck_err o r b i t, c f r1<24>. th e a u t o ma t i c syn c hr o n i z a t ion f u n c t i on is enab le d b y s e t t in g t h e c o n t r o l f u n c t i o n reg i s ter 1 a u t o ma t i c s y n c hr o n iza t ion b i t, cfr1<3>. t o em plo y t h is f u n c t i on a t hig h er clo c k ra t e s (s yn c_ clk > 62.5 mh z and s y sclk > 250 mh z), t h e hig h s p ee d sy n c ena b le b i t (cfr 1<0>) sh o u ld b e s et as we l l . man ual sync h r onization, h a r d ware cont rolled i n th i s m o de , th e use r co n t r o ls th e tim i n g r e la tio n s h i p o f t h e s y n c _ c l k w i t h re sp e c t to s y s c l k . whe n h a r d w a re m a n u a l syn c hr o n i z a t ion is ena b le d , t h e p ll_l o ck/ s y n c _i n p i n beco m e s a d i g i t a l i n p u t . f o r ea c h a n d ev e r y ri s i n g ed g e d e t e ct e d o n t h e s y n c _i n in p u t, t h e de v i ce ad v a nces t h e s y n c _in r i sin g e d g e b y o n e s y scl k p e r i o d . w h en t h is b i t is enab le d , t h e p ll_l o ck is no t a v a i la b l e as an o u t p u t . h o w e v e r , a n o u t-o f - lo ck co ndi t i o n c a n b e de te c t e d b y r e adin g c o n t rol f u n c t i o n reg i st er 1 an d ch ec k i n g t h e sta t us o f th e p ll l o c k er r o r b i t , c f r 1 < 24> . th i s syn c h r o n iz a t io n fun c t i o n i s en a b led b y set t in g t h e ha rd wa r e ma n u al sy n c hr o n i z a t ion enab le b i t, cfr1<1>. manual synchronization, so ftware contro lled i n th i s m o de , th e use r co n t r o ls th e tim i n g r e la tio n s h i p bet w een sy n c _ c l k a n d sy s c l k t h r o u g h s o f t w a r e p r o g r a m m i n g . w h en t h e s o f t w a r e ma n u al sy n c hr o n iza t ion b i t (cfr1<2>) is s et hig h , t h e s y n c _cl k is ad v a n c e d b y on e s y sclk c y cle . on ce t h is o p era t io n is com p let e , t h e b i t is cle a r e d . th e us er can s et t h is b i t r e p e a t e d ly t o ad vance t h e s y n c _c lk r i sin g e d g e m u l t i p le t i m e s. b e ca us e t h e o p e r a t io n do es n o t us e t h e pll_lo ck / s y n c _i n p i n as a s y nc_in in pu t , t h e pll_lo ck sig n a l can b e m o ni to r e d o n t h e pl l_lo c k p i n d u r i n g t h is o p er a t io n . sy sc lk d u t 1 s y nc cl k du t1 s y n c c l k d u t 2 without s y nc _ c l k al i g n e d sy sc lk d u t 2 synchr o n i z at i o n f u nct i o ns c a n al i g n d i g i t al cl o c k r e l a t i onshi ps, t h ey c a n n o t des k ew t h e e d g es of c l ocks s y n c c l k d u t 2 with s y nc _ c l k al i g n e d 01 2 30 01 2 3 3 04806-0-003 f i gure 28. s y nch r oniz ation f u nc tion s : c a p a bi li t i e s a n d l i m i ta t i on s
AD9956 rev. 0 | page 22 of 32 serial port opera t ion an AD9956 s e r i al da ta-p o r t comm unica t io n c y c l e has tw o phas es. phas e 1 is t h e i n st r u c t io n c y cle , w h ich is t h e wr i t i n g o f a n inst r u c t io n b y t e t o t h e a d 99 56, co in cide n t wi t h t h e f i rst eig h t s c lk r i si n g e d g e s. th e ins t r u c t io n b y t e pr o v ides t h e AD9956 s e r i al p o r t co n t r o l l er wi t h inf o r m a t ion r e ga r d in g t h e da ta tra n s f e r c y c l e , wh i c h i s p h a s e 2 o f t h e c o m m u n i c a t i o n c y c l e . th e p h as e 1 in s t r u c t i o n b y t e de f i n e s w h et h e r t h e u p co min g d a t a t r a n sfer is r e ad o r wr i t e and t h e s e r i al addr es s of t h e re g i ste r b e ing a c c e ss e d . the f i rs t eig h t s c lk r i sin g e d g e s o f e a ch co mm unica t io n c y cle a r e us ed t o wr i te th e in s t r u c t io n b y t e in t o t h e AD9956. th e r e ma inin g s c l k e d g e s a r e fo r p h as e 2 o f t h e c o mm uni c a t io n c y c l e . p h as e 2 is th e ac t u al da t a tra n sf er between the AD9956 a nd t h e sys t e m co n t r o l l er . th e n u m b er o f b y t e s t r a n sfer r e d d u r i n g p h as e 2 o f t h e co mm uni c a t ion c y cle is a f u n c t i on o f t h e r e g i s t e r bein g ac ces s ed . f o r e x a m p l e , wh en acces s i n g c o n t r o l f u nc t i on r e g i ster 2, w h ich is four b y t e s w i d e , ph a s e 2 re qu ires t h a t fo u r b y t e s be tra n sfe r r e d . i f ac ces s in g a f r e q uen c y t u n i n g w o r d , w h ich is s i x b y tes wide , p h as e 2 r e q u ir es t h a t si x b y t e s b e tra n s f e r r e d . a f t e r tra n s f e r ri n g all d a ta b y t e s pe r th e in s t r u cti o n , t h e comm un ic a t io n c y cle is co m p let e d . a t th e com p letio n o f a n y co mm unic a t ion c y c l e , th e AD9956 se ri al po r t c o n t r o l l e r e x pect s th e n e xt ei gh t ri s i n g s c l k ed g e s t o b e t h e i n st r u c t io n b y t e o f t h e n e xt comm un ica t ion c y cle . a l l da ta in p u t t o t h e AD9956 is r e g i s t er ed on t h e r i sin g edg e o f sclk. al l da ta is dr i v en o u t o f t h e AD9956 on t h e fal l in g edge of s c l k . f i g u re 2 9 t h rou g h f i g u re 3 2 are u s e f u l i n u n d e r s t a n d - in g the g e n e ral o p era t ion o f th e AD9956 s e r i al p o r t . 04806-0-004 i 6 i 5 i 4 i 3 i 2 i 1 d 5 d 4 d 3 d 2 d 1 d 0 i 0 d 7 d 6 i 7 instruction cycle s cl k s di/o data transfer cycle cs f i g u re 29. s e ri al p o r t writ e ti ming c lo ck st a ll l o w 04806-0-005 i 6 i 5 i 4 i 3 i 2 i 1 i 0 don't care i 7 instruction cycle s cl k s di/o data transfer cycle d o 5 d o 4 d o 3 d o 2 d o 1 d o 0 d o 7 d o 6 sdo cs f i g u re 30. 3-w i r e s e ri al p o r t r e ad ti m i ng c l o ck st a l l l o w 04806-0-006 i 6 i 5 i 4 i 3 i 2 i 1 d 5 d 4 d 3 d 2 d 1 d 0 i 0 d 7 d 6 i 7 instruction cycle s cl k s di/o data transfer cycle cs f i g u re 31. s e ri al p o r t writ e ti ming c lo ck st a ll hig h 04806-0-007 i 6 i 5 i 4 i 3 i 2 i 1 d o 5 d o 4 d o 3 d o 2 d o 1 d o 0 i 0 d o 7 d o 6 i 7 instruction cycle s cl k s di/o data transfer cycle cs f i g u re 32. 2-w i r e s e ri al p o r t r e ad ti m i ng c l o ck st a l l h i g h
AD9956 rev. 0 | page 23 of 32 instruc t i o n b y te the inst r u c t io n b y t e co n t a i n s t h e fol l o w in g info r m a t io n: t a bl e 4. d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 r / w b x x a 4 a 3 a 2 a 1 a 0 r/wbb i t 7 o f t h e i n s t r u c t io n b y t e det e r m i n es w h et her a r e ad or w r i t e d a t a t r ans f e r o c c u rs af te r t h e i n st r u c t i o n b y te w r i te. l o g i c 1 indic a te s a r e ad o p er a t i o n. l o g i c 0 i n di ca te s a wr i t e op e r a t i o n . x, xb i ts 6 and 5 o f t h e i n s t r u c t io n b y t e a r e d o n t c a r e . a 4 to a 0 b it s 4 to 0 of t h e i n s t r u c t i o n b y te de te r m i n e w h i c h r e gi s t e r i s a cce s s ed d u ri n g th e da ta tra n s f e r po r t i o n o f th e co mm unic a t io ns c y c l e . serial interf a c e port pin description s c l k s e r i a l cl oc k . t h e se ri al c l oc k p i n i s u s ed t o s y n c h r o n i z e da ta t o a nd f r o m the AD9956 a nd t o r u n the in t e r n al s t a te machi n es. t h e sclk max i m u m f r e q uen c y is 25 mh z. cs chi p s e lec t b a r . cs is a n ac t i v e l o w in p u t tha t al lo ws m o r e tha n o n e de vice o n the s a m e s e r i al co mm unica t io n s lin e . th e s d o and s d i/ o p i n s go to a h i g h i m p e dance st a t e w h e n t h is in p u t is hig h . i f dr i v en hig h d u r i n g an y co mm u n ica t io n s c y cle , t h a t c y cle is susp ende d un t i l cs i s r e a c ti v a t e d lo w . ch i p se lec t ca n be t i ed lo w i n s y s t em s th a t m a i n ta in co n t r o l o f sc l k . sdi / o s e r i a l d a t a in put / o u tput . d a t a i s a l w a y s w r it te n to t h e AD9956 o n this p i n. h o w e v e r , t h is p i n can b e us ed as a b i dir e c - ti o n al da t a lin e . c f r 1 < 7 > co n t r o l s th e co n f i g ura t i o n o f th i s p i n. the def a u l t val u e (0) co nf igur es t h e s d i / o p i n as b i dir e c t io nal. sd o s e r i a l d a t a o u t . d a t a i s re a d f rom t h i s pi n f o r proto c o l s th a t use se pa ra t e li n e s f o r tra n sm i t ti n g a n d r e ce i v i n g d a ta . w h e n th e ad 9956 o p era t e s in a s i n g le b i di r e ct i o nal i/o m o de , th is p i n d o es n o t o u t p u t da t a a n d is set to a hi g h im p e da n c e st a t e. i/o_res e t a hig h sig n al on t h is p i n r e s e ts t h e i/o p o r t s t a te machi n es wi t h ou t a f fe c t in g t h e addr es s a b l e reg i s t ers co n t en ts. an ac t i v e hig h i n p u t on t h e i/o _ res e t p i n c a us es t h e c u r r en t co mm uni c a t io n c y cle t o a b o r t. af t e r i/o_res e t r e t u r n s lo w ( 0 ) , a n o t h e r comm uni c a t io n c y cle ca n b e g i n, st a r t i n g w i t h t h e i n st r u c t i o n b y te w r i te. n o te t h a t w h e n not i n u s e, t h i s pi n s h o u ld b e f o r c ed lo w , be ca us e i t f l o a ts t o th e thr e s h o l d val u e . msb/lsb tr ansfers the AD9956 s e r i al p o r t ca n s u p p o r t bo th m o st sig n if ican t b i t (ms b ) f i rs t o r le as t sig n if i c a n t b i t (ls b ) f i rs t da t a fo r m a t s. thi s fun c ti o n ali t y i s co n t r o lled b y th e l s b f i r s t b i t i n c o n t r o l reg i st er 1 (cfr 1<15>). th e def a u l t val u e o f t h i s b i t is lo w (ms b f i rs t). w h en cfr1 <15 > is s et hig h , th e AD9956 s e r i al p o r t is in ls b f i rst fo r m a t . th e i n st r u c t io n b y t e m u st b e wr i t t e n in t h e f o r m a t indic a t e d b y cfr1 <15>. i f th e AD9956 is in l s b f i rs t m o de , t h e i n s t r u c t io n b y t e m u s t b e wr i t t e n f r o m le as t sig n if ica n t b i t to m o s t sig n if i c an t b i t . h o we v e r , t h e i n s t r u c t io n b y t e phas e o f t h e co mm u n ic a t ion s c y cle s t i l l p r e c e d es t h e da t a tra n s f e r c y c l e . f o r ms b f i rst o p er a t ion, a l l d a t a wr i t te n to ( r e a d f r o m ) t h e AD9956 a r e in ms b f i rs t o r d er . i f th e ls b mo de is ac ti v e , al l da ta wr i t t e n t o ( r ead f r o m ) th e AD9956 a r e in ls b f i rs t o r d er . cs scl k sdi/o t pre t dsu t sclkw t dhld second bit first bit symbol t pre t sclkw t dsu t dhld min 6ns 40ns 6.5ns 0ns definition cs setup time period of serial data clock (write) serial data setup time serial data hold time 04806-0-034 f i g u re 33. ti m i ng d i ag r a m f o r d a t a writ e t o a d 9 9 56 t dv first bit second bit sdi/o sdo sclk cs symbol t dv t sclkr max 40ns 400ns definition data valid time period of serial data clock (read) 04806-0-035 t sclkr f i g u re 34. ti m i ng d i ag r a m f o r d a t a r e ad t o a d 9 9 56
AD9956 rev. 0 | page 24 of 32 register map and description table 5. register name (serial address) bit range (msb) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value/ profile <31:24> open 1 open 1 open 1 open 1 open 1 open 1 open 1 pll lock error 0x00 <23:16> load srr @ i/o_update auto-clr frequency accum. auto- clr phase accum. enable sine output clear frequency accum. clear phase accum. linear sweep enable linear sweep no dwell 0x00 <15:8> lsb first sdi/o input only open 1 open 1 open 1 open 1 open 1 open 1 0x00 control function register 1 (cfr1) (0x00) <7:0> digital power- down pfd input power- down pllref crystal enable sync_clk disable auto sync multiple AD9956s software manual sync hardware manual sync high speed sync enable 0x00 <39:32> dac power- down open 1 open 1 open 1 open 1 open 1 internal band gap power- down internal cml driver drv_rset 0x00 <31:24> clock driver rising edge <31:29> clock driver falling edge control <28:26> pll lock detect enable pll lock detect mode 0x00 <23:16> rf divider power- down rf divider ratio <22:21> clock driver power- down clock driver input select <19:18> slew rate control rf div refclk mux bit 0x78 <15:8> divider m control <15:12> divider n control <11:8> 0x00 control function register 2 (cfr2) (0x01) <7:0> open 1 open 1 cp polarity cp full pd cp quick pd cp current scale <2:0> 0x07 <23:16> rising delta frequency tuning word <23:16> 0x00 <15:8> rising delta frequency tuning word <15:8> 0x00 rising delta frequency tuning word (rdftw) (0x02) <7:0> rising delta frequency tuning word <7:0> 0x00 <23:16> falling delta frequency tuning word <23:16> 0x00 <15:8> falling delta frequency tuning word <15:8> 0x00 falling delta frequency tuning word (fdftw) (0x03) <7:0> falling delta frequency tuning word <7:0> 0x00 <15:8> rising sweep ramp rate <15:8> 0x00 rising sweep ramp rate (rsrr) (0x04) <7:0> rising sweep ramp rate <7:0> 0x00 <15:8> rising sweep ramp rate <15:8> 0x00 falling sweep ramp rate (fsrr) (0x05) <7:0> rising sweep ramp rate <7:0> 0x00 1 in all cases, open bits must be written to 0.
AD9956 rev. 0 | page 25 of 32 register name (serial address) bit range (msb) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value/ profile <63:56> open 1 phase offset word 0 (pow0) <13:8> 0x00 <55:48> phase offset word 0 (pow0) <7:0> 0x00 <47:40> frequency tuning wo rd 0 (ftw0) <47:40> 0x00 <39:32> frequency tuning wo rd 0 (ftw0) <39:32> 0x00 <31:24> frequency tuning wo rd 0 (ftw0) <31:24> 0x00 <23:16> frequency tuning wo rd 0 (ftw0) <23:16> 0x00 <15:8> frequency tuning wo rd 0 (ftw0) <15:8> 0x00 profile control register no. 0 (pcr0) (0x06) <7:0> frequency tuning word 0 (ftw0) <7:0> 0x00 <63:56> open 1 phase offset word 1 (pow1) <13:8> 0x00 <55:48> phase offset word 1 (pow1) <7:0> 0x00 <47:40> frequency tuning wo rd 1 (ftw1) <47:40> 0x00 <39:32> frequency tuning wo rd 1 (ftw1) <39:32> 0x00 <31:24> frequency tuning wo rd 1 (ftw1) <31:24> 0x00 <23:16> frequency tuning wo rd 1 (ftw1) <23:16> 0x00 <15:8> frequency tuning wo rd 1 (ftw1) <15:8> 0x00 profile control register no. 1 (pcr1) (0x07) <7:0> frequency tuning word 1 (ftw1) <7:0> 0x00 <63:56> open 1 phase offset word 2 (pow2) <13:8> 0x00 <55:48> phase offset word 2 (pow2) <7:0> 0x00 <47:40> frequency tuning wo rd 2 (ftw1) <47:40> 0x00 <39:32> frequency tuning wo rd 2 (ftw2) <39:32> 0x00 <31:24> frequency tuning wo rd 2 (ftw2) <31:24> 0x00 <23:16> frequency tuning wo rd 2 (ftw2) <23:16> 0x00 <15:8> frequency tuning wo rd 2 (ftw2) <15:8> 0x00 profile control register no. 2 (pcr2) (0x08) <7:0> frequency tuning word 2 (ftw2) <7:0> 0x00 <63:56> open 1 phase offset word 3 (pow3) <13:8> 0x00 <55:48> phase offset word 3 (pow3) <7:0> 0x00 <47:40> frequency tuning wo rd 3 (ftw3) <47:40> 0x00 <39:32> frequency tuning wo rd 3 (ftw3) <39:32> 0x00 <31:24> frequency tuning wo rd 3 (ftw3) <31:24> 0x00 <23:16> frequency tuning word. 3 (ftw3) <23:16> 0x00 <15:8> frequency tuning wo rd 3 (ftw3) <15:8> 0x00 profile control register no. 3 (pcr3) (0x09) <7:0> frequency tuning word 3 (ftw3) <7:0> 0x00 1 in all cases, open bits must be written to 0.
AD9956 rev. 0 | page 26 of 32 register name (serial address) bit range (msb) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value/ profile <63:56> open 1 phase offset word 4 (pow4) <13:8> 0x00 <55:48> phase offset word 4 (pow4) <7:0> 0x00 <47:40> frequency tuning wo rd 4 (ftw4) <47:40> 0x00 <39:32> frequency tuning wo rd 4 (ftw4) <39:32> 0x00 <31:24> frequency tuning wo rd 4 (ftw4) <31:24> 0x00 <23:16> frequency tuning wo rd 4 (ftw4) <23:16> 0x00 <15:8> frequency tuning wo rd 4 (ftw4) <15:8> 0x00 profile control register no. 4 (pcr4) (0x0a) <7:0> frequency tuning word 4 (ftw4) <7:0> 0x00 <63:56> open 1 phase offset word 5 (pow5) <13:8> 0x00 <55:48> phase offset word 5 (pow5) <7:0> 0x00 <47:40> frequency tuning wo rd 5 (ftw5) <47:40> 0x00 <39:32> frequency tuning wo rd 5 (ftw5) <39:32> 0x00 <31:24> frequency tuning wo rd 5 (ftw5) <31:24> 0x00 <23:16> frequency tuning wo rd 5 (ftw5) <23:16> 0x00 <15:8> frequency tuning wo rd 5 (ftw5) <15:8> 0x00 profile control register no. 5 (pcr5) (0x0b) <7:0> frequency tuning word 5 (ftw5) <7:0> 0x00 <63:56> open 1 phase offset word 6 (pow6) <13:8> 0x00 <55:48> phase offset word 6 (pow6) <7:0> 0x00 <47:40> frequency tuning wo rd 6 (ftw6) <47:40> 0x00 <39:32> frequency tuning wo rd 6 (ftw6) <39:32> 0x00 <31:24> frequency tuning wo rd 6 (ftw6) <31:24> 0x00 <23:16> frequency tuning wo rd 6 (ftw6) <23:16> 0x00 <15:8> frequency tuning wo rd 6 (ftw6) <15:8> 0x00 profile control register no. 6 (pcr6) (0x0c) <7:0> frequency tuning word 6 (ftw6) <7:0> 0x00 <63:56> open 1 phase offset word 7 (pow7) <13:8> 0x00 <55:48> phase offset word 7 (pow7) <7:0> 0x00 <47:40> frequency tuning wo rd 7 (ftw7) <47:40> 0x00 <39:32> frequency tuning wo rd 7 (ftw7) <39:32> 0x00 <31:24> frequency tuning wo rd 7 (ftw7) <31:24> 0x00 <23:16> frequency tuning wo rd 7 (ftw7) <23:16> 0x00 <15:8> frequency tuning wo rd 7 (ftw7) <15:8> 0x00 profile control register no. 7 (pcr7) (0x0d) <7:0> frequency tuning word 7 (ftw7) <7:0> 0x00 1 in all cases, open bits must be written to 0.
AD9956 rev. 0 | page 27 of 32 control function register descriptions control function register 1 (cfr1) this control register is comprised of four bytes, all of which must be written during a write operation involving cfr1. cfr1 is used to control various functions, features, and operating modes of the AD9956. the functionality of each bit(s) is described below. in general, the bit is named for the function it serves when the bit is set. cfr1<31:25> open. unused locations. write a logic 0 cfr1<24> pll lock error (read-only) when the device is operating in automatic synchronization mode or hardware manual synchronization mode (see below), the pll_lock/ sync_in pin behaves as the sync_in. to determine whether or not the pll has become unlocked while in synchronization mode, this bit serves as a flag to indicate that an unlocked condition has occurred within the phase frequency detector. once set, the flag stays high until it is cleared by a readback of the value even though the loop might have relocked. readback of the cfr1 register clears this bit. cfr1<24> = 0 indicates that the loop has maintained lock since the last readback. cfr1<24> = 1 indicates that the loop became unlocked at some point since the last readback of this bit. cfr1<23> load sweep ramp rate at i/o_update, also known as load srr @ i/o_update the sweep ramp rate is set by entering a value to a down counter that is clocked by the sync_clk. each time a new step is taken in the linear sweep algorithm, the ramp rate value is passed from the linear sweep ramp rate register to this down counter. when set, cfr1<23>, enables the user to force the part to restart the countdown sequence for the current linear sweep step by toggling the i/o_update pin. cfr1<23> = 0 (default). the linear sweep ramp rate countdown value is loaded only upon completion of a countdown sequence. cfr1<23> = 1. the linear sweep ramp rate countdown value is reloaded, if an i/o_update signal is sent to the part during a sweep. cfr1<22> auto-clear frequency accumulator this bit enables the auto-clear function for the frequency accu- mulator. the auto-clear function serves as a clear and release func- tion for the frequency accumulator (which performs the linear sweep operation), which then begins sweeping from a known value of ftw0. cfr1 <22> = 0 (default). issuing an i/o_update has no effect on the current state of the frequency accumulator. cfr1 <22> = 1. issuing an i/o_update signal to the part clears the current contents of the frequency accumulator for one sync-clock period. cfr1 <21> auto-clear phase accumulator this bit enables the auto-clear function for the phase accumula- tor. the auto-clear function serves as a reset function for the phase accumulator, which then begins accumulating from a known phase value of 0. cfr1<21> = 0 (default). issuing an i/o_update has no effect on the current state of the phase accumulator. cfr1<21> = 1. issuing an i/o_update clears the current con- tents of the phase accumulator for one sync_clk period. cfr1 <20> enable sine output two different trigonometric functions can be used to convert the phase angle to an amplitude value, cosine or sine. this bit selects the function used. cfr1<20> = 0 (default). the phase-to-amplitude conversion block uses a cosine function. cfr1<20> = 1. the phase-to-amplitude conversion block uses a sine function. cfr1 <19> clear frequency accumulator this bit serves as a static-clear or a clear-and-hold bit for the frequency accumulator. it prevents the frequency accumulator from incrementing the value as long as it is set. cfr1 <19> = 0 (default). the frequency accumulator operates normally. cfr1 <19> = 1. the frequency accumulator is cleared and held at a value of 0. cfr1 <18> clear phase accumulator this bit serves as a static-clear or a clear-and-hold it for the phase accumulator. it prevents the phase accumulator from incrementing the value as long as it is set. cfr1 <18> = 0 (default). the phase accumulator operates normally. cfr1 <18> = 1. the phase accumulator is cleared and held at a value of 0.
AD9956 rev. 0 | page 28 of 32 cfr1 <17> linear sweep enable this bit turns on the frequency accumulator, which enables the dds to perform linear sweeping. cfr1<17> = 0 (default). the dds generates frequencies in single-tone mode. cfr1<17> = 1. the dds uses the frequency accumulator to sweep the frequency tuning word being sent to the phase accumulator according to the values set in the delta frequency tuning word and delta frequency ramp rate registers. for a detailed explanation of this mode, see the linear sweep mode of operation section. cfr1 <16> linear sweep no dwell this bit dictates the behavior of the dds core upon completion of a linear sweep. cfr1<16> = 0 (default). upon reaching the upper value of the sweep (ftw1), the dds holds at the frequency value stored in ftw1. cfr1<16> = 1. upon reaching the upper value of the sweep (ftw1), the dds returns to the initial value in the sweep (ftw0) and continues to output that frequency until a new sweep is initiated (by bringing ps0 low and then high). cfr1 <15> lsb first serial data mode the serial data transfer to the device can be either msb first or lsb first. this bit controls that operation. cfr1<15> = 0 (default). serial data transfer to the device is in msb first mode. cfr1<15> = 1. serial data transfer to the device is in lsb first mode. cfr1<14> sdi/o input only (3-wire serial data mode) the serial port on the AD9956 can act in 2-wire mode (sclk and sdi/o) or 3-wire mode (sclk, sdi/o, and sdo). this bit toggles the serial port between these two modes. cfr1<14> = 0 (default). serial data transfer to the device is in 2-wire mode. the sdi/o pin is bidirectional. cfr1<14> = 1. serial data transfer to the device is in 3-wire mode. the sdi/o pin is input only. cfr1<13:8> open unused locations. write a logic 0. cfr1<7> digital power-down this bit powers down the digital circuitry not directly related to the i/o port. the i/o port functionality is not suspended, re- gardless of the state of this bit. cfr1<7> = 0 (default). digital logic operating as normal. cfr1<7> = 1. all digital logic not directly related to the i/o port is powered down. internal digital clocks are suspended. cfr1<6> phase frequency detector input power-down this bit controls the input buffers on the phase frequency detec- tor. it provides a way to gate external signals from the phase frequency detector itself. cfr1<6> = 0 (default). phase frequency detector input buffers are functioning normally. cfr1<6> = 1. phase frequency detector input buffers are pow- ered down, isolating the phase frequency detector from the outside world. cfr1<5> pllref crystal enable the AD9956 phase frequency detector has an on-chip oscillator circuit. when enabled, the reference input to the phase fre- quency detector (pllref/ pllref ) can be driven by a crystal. cfr1<5> = 0 (default). phase frequency detector reference input operates as a standard analog input. cfr1<5> = 1. reference input oscillator circuit is enabled, allowing the use of a crystal for the reference of the phase frequency detector. cfr1<4> sync_clk disable if synchronization of multiple devices is not required, the spec- tral energy resulting from this signal can be reduced by gating the output buffer off. this function gates the internal clock ref- erence sync_clk (sysclk/4) off of the sync_out pin. cfr1<4> = 0 (default). sync_clk signal is present on the sync_out pin and is ready to be ported to other devices. cfr1<4> = 1. sync_clk signal is gated off, putting the sync_out pin into a high impedance state. cfr1<3> automatic synchronization one of the synchronization modes of the AD9956 forces the dds core to derive the internal reference from an external ref- erence supplied on the sync_in pin. for details on synchroni- zation modes for the dds core, see the synchronization modes for multiple devices section.
AD9956 rev. 0 | page 29 of 32 cfr1<3> = 0 (default). the automatic synchronization function of the dds core is disabled. cfr1<3> = 1. the automatic synchronization function is on. the device is slaved to an external reference and adjusts the internal sync_clk to match the external reference, which is supplied on the sync_in input. cfr1<2> software manual synchronization rather than relying on the part to automatically synchronize the internal clocks, the user can program the part to advance the internal sync_clk one system clock cycle. this bit is self clearing and can be set multiple times. cfr1<2> = 0 (default). the sync_clk stays in the current timing relationship to sysclk. cfr1<2> = 1. the sync_clk advances the rising and falling edges by one sysclk cycle. this bit is then self-cleared. cfr1<1> hardware manual synchronization similar to the software manual synchronization (cfr1<2>), this function enables the user to advance the sync_clk rising edge by one system clock period. this bit enables the pll_lock/sync_in pin as a digital input. once enabled, every rising edge on the sync_in input advances the sync_clk by one sysclk period. while enabled, the pll_lock signal is not available on an external pin. however, loop out-of-lock events trigger a flag in the control register (cfr1<24>). cfr1<1> = 0 (default). the hardware manual synchronization function is disabled. either the part is outputting the pll_lock (cfr1<3> = 0), or it is using the sync_in to slave the sync_clk signal to an external reference provided on sync_in (cfr1<3> = 1). cfr1<1> = 1. pll_lock/sync_in is set as a digital input. each subsequent rising edge on this pin advances the sync_clk rising edge by one sysclk period. cfr1<0> high speed synchronization enable bit this bit enables extra functionality in the auto synchronization algorithm, which enables the device to synchronize high speed clocks (sync_clk > 62.5 mhz). cfr1<0> = 0 (default). high speed synchronization is disabled. cfr1<0> = 1. high speed synchronization is enabled. control function register 2 (cfr2) this control register is comprised of five bytes, which must be written during a write operation involving cfr2. with some minor exceptions, the cfr2 primarily controls analog and tim- ing functions on the AD9956. cfr2<39> dac power-down bit this bit powers down the dac portion of the AD9956 and puts it into the lowest power dissipation state. cfr2<39> = 0 (default). dac is powered on and operating. cfr2<39> = 1. dac is powered down and the output is in a high impedance state. cfr2<38> to cfr2<34> open unused locations. write a logic 0. cfr2<33> internal band gap power-down to shut off all internal quiescent current , the band gap needs to be powered down. this is normally not done because it takes a long time (~10 ms) for the band gap to power up and settle to its final value. cfr2<33> = 0. even when all other sections are powered down, the band gap is powered up and is providing a regulated voltage. cfr2<33> = 1. the band gap is powered down. cfr2<32> internal cm l driver drv_rset to program the cml drivers output current, a resistor must be placed between the drv_rset pin and ground. this bit enables an internal resistor to program the output current of the driver. cfr2<32> = 0 (default). the drv_rset pin is enabled, and an external resistor must be attached to the cp_rset pin to program the output current. cfr2<32> = 1. the cml current is programmed by the inter- nal resistor and ignores the resistor on the drv_rest pin. cfr2<31:29> clock driver rising edge these bits control the slew rate of the cml clock driver outputs rising edge. when these bits are on, additional current is sent to the output driver to increase the rising edge slew rate capability; the contributions of each bit are cumulative. table 6 describes how the bits increase the current. note that the additional cur- rent is on only during the rising edge of the waveform for ap- proximately 250 ps, but not on during the entire transition. table 6. cml clock driver rising edge slew rate control bits and associated surge current cfr2<31> = 1 7.6 ma cfr2<30> = 1 3.8 ma cfr2<29> = 1 1.9 ma
AD9956 rev. 0 | page 30 of 32 cfr2<28:26> clock driver falling edge control these bits control the slew rate of the cml clock driver outputs falling edge. when these bits are on, additional current is sent to the output driver to increase the rising edge slew rate capability. table 7 describes how the bits increase the current; the contri- butions of each bit are cumulative. note that the additional cur- rent is on only during the rising edge of the waveform, for ap- proximately 250 ps, but not on during the entire transition. table 7. cml clock drive falling edge slew rate control bits and associated surge current cfr2<28> = 1 5.4 ma cfr2<30> = 1 2.7 ma cfr2<29> = 1 1.35 ma cfr2<25> pll_lock_detect enable this bit enables the pll_lock/sync_in pin as a lock detect output for the pll. cfr2<25> = 0 (default).the pll_lock_detect signal is disabled. cfr2<25> = 1. the pll_lock_detect signal is enabled. cfr2<24> pll_lock_detect mode this bit toggles the modes of the pll_lock_detect func- tion. the lock detect can either be a status indicator (locked or unlocked), or it can indicate a lead-lag relationship between the two phase frequency detector inputs. cfr2<24> = 0 (default). the lock detect acts as a status indica- tor (pll is locked 0 or unlocked 1). cfr2<24> = 1. the lock detect acts as a lead/lag indicator. a 1 on the pll_lock pin means that the pllosc pin lags the reference. a 0 means that the pllosc pin leads the reference. cfr2<23> rf divider power-down this bit powers the rf divider down to save power when not in used. cfr2<23> = 0 (default). rf divider is on. cfr2<23> = 1. rf divider is powered down and an alternate path between the refclk inputs and sysclk is enabled. cfr2<22:21> rf divider ratio these two bits control the rf divider ratio (r). cfr2<22:21> = 11 (default). rf divider r = 8. cfr2<22:21> = 10. rf divider r= 4. cfr2<22:21> = 01. rf divider r = 2. cfr2<22:21> = 00. rf divider r = 1. note that this is not the same as bypassing the rf divider. cfr2<20> clock driver power-down this bit powers down the cml clock driver circuit. cfr2<20> =1 (default). cml clock driver circuit is powered down. cfr2<20> = 0. cml clock driver is powered up. cfr2<19:18> clock driver input select these bits control the mux on the input for the cml clock driver. cfr2<19:18> = 00. the cml clock driver is disconnected from all inputs (and does not toggle). cfr2<19:18> = 01. the cml clock driver is driven by the pllosc input pin. cfr2<19:18> = 10 (default). the cml clock driver is driven by the output of the rf divider. cfr2<19:18> = 11. the cml clock driver is driven by the input of the rf divider cfr2<17> slew rate control bit even without the additional surge current supplied by the rising edge slew rate control bits and the falling edge slew rate control bits, the device applies a default 7.6 ma surge current to the rising edge and a 4.05 ma surge current to the falling edge. this bit disables all slew rate enhancement surge current, including the default values. cfr2<17> = 0 (default). the cml driver applies default surge current to rising and falling edges. cfr2<17> = 1. driver applies no surge current during transi- tions. the only current is the continuous current. cfr2<16> rf divider sysclk mux bit this bit toggles the mux to control whether the rf divider out- put or input is supplying sysclk to the device. cfr2<16> = 0 (default). the rf divider output supplies the dds sysclk. cfr2<16> = 1. the rf divider input supplies the dds sysclk (bypass the divider). note that regardless of the condition of the configuration of the clock input, the dds sysclk must not exceed the maximum rated clock speed.
AD9956 rev. 0 | page 31 of 32 cfr2<15:12> pllref divider control bits (m) these 4 bits set the pllref divider (m) ratio where m is a value equal to 1 to 16. cfr2<15:12> = 0000 means that m = 1 and cfr2<15:12> = 1111 means that m = 16, or simply, m = cfr2<15:12> + 1. cfr2<15:12> = m = cfr2<15:12> = m = 0000 1 1000 9 0001 2 1001 10 0010 3 1010 11 0011 4 1011 12 0100 5 1100 13 0101 6 1101 14 0110 7 1110 15 0111 8 1111 16 cfr2<11:8> pllref divider control bits (n) these 4 bits set the pllosc divider (n) ratio where n is a value equal to 1 to 16. cfr2<11:8> = 0000 means that n = 1 and cfr2<11:8> = 1111 means that n = 16, or n = cfr2<11:8> + 1. cfr2<15:12> = n = cfr2<11:8> = n = 0000 1 1000 9 0001 2 1001 10 0010 3 1010 11 0011 4 1011 12 0100 5 1100 13 0101 6 1101 14 0110 7 1110 15 0111 8 1111 16 cfr2<7:6> open unused locations. write a logic 0. cfr2<5> cp polarity this bit sets the polarity of the charge pump, in response to a ground referenced or a supply referenced vco. cfr2<5> = 0 (default). the charge pump is configured to operate with a supply referenced vco. if pllosc lags pllref, the charge pump will attempt to drive the vco control node voltage higher. if pllosc leads pllref, the charge pump will attempt to drive the vco control node voltage lower. cfr2<5> = 1. the charge pump is configured to operate with a ground referenced vco. if pllosc lags pllref, the charge pump will attempt to drive the vco control node voltage lower. if pllosc leads pllref, the charge pump will attempt to drive the vco control node voltage higher. cfr2<4> charge pump full power-down this bit, when set, will put the charge pump into a full power- down mode. cfr2<4> = 0 (default). the charge pump is powered on and operating normally. cfr2<4> = 1. the charge pump is completely powered down. cfr2<3> charge pump quick power-down rather than power down the charge pump, which can take a long time to recover from, a quick power-down mode, which powers down only the charge pump output buffer, is included. while this doesnt reduce the power consumption significantly, it does shut off the output to the charge pump and allows it to come back on in a rapidly. cfr2<3> = 0 (default). the charge pump is powered on and operating normally. cfr2<3> = 1. the charge pump is on and running, but the output buffer is powered down. cfr2<2:0> charge pump current scale. a base output current from the charge pump is determined by a resistor connected from the cp_rset pin to ground (see the pll circuitry section). however, it is possible to multiply the charge pump output current by a value from 1:8 by programming these bits. the charge pump output current are scaled by cfr2<2:0> +1. cfr2<2:0> = 000 (default). scale factor = 1 to cfr2<2:0> = 111 (8). cfr2<2:0> scale factor 000 1 001 2 010 3 011 4 100 5 101 6 110 7 111 8
AD9956 rev. 0 | page 32 of 32 outline dimensions pin 1 indicator top view 6.75 bsc sq 7.00 bsc sq 1 48 12 13 37 36 24 25 5.25 5.10 sq 4.95 0.50 0.40 0.30 0.30 0.23 0.18 0.50 bsc 12 max 0.20 ref 0.80 max 0.65 typ 1.00 0.85 0.80 5.50 ref 0.05 max 0.02 nom 0.60 max 0.60 max pin 1 indicator coplanarity 0.08 seating plane 0.25 min exposed pad (bo tt om view) compliant to jedec standards mo-220-vkkd-2 f i gure 35. 4 8 -l ead l e ad f r a m e ch ip s c a l e p a ck ag e [lfcs p ] 7 mm 7 m m b o d y (cp - 4 8 ) di me nsio ns sho w n i n mi ll im e t e r s ordering guide model temperature r a nge package descri ption package option AD9956ycpz 1 C40c to +125c 48-lead lead fr ame chip scale package (lfcsp) cp-48 AD9956ycpz-reel 1 C40c to +125c 48-lead lead fr ame chip sc ale package (lfcsp), tape and reel cp-48 a d 9 9 5 6 / p c b e v a l u a t i o n boar d 1 z = pb-free part. ? 2004 a n alo g devic e s, inc. all rig h ts res e rve d . t r ade m arks a n d re g i s - tered trade m arks are the property of their respective owners . d04806C0C 7/04(0)

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